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1. general description the 74lvt125; 74lvth125 is a high-performance bicmos product designed for v cc operation at 3.3 v. this device combines low static and dynamic power dissipation with high speed and high output drive. the 74lvt125; 74lvth125 device is a quad buffer that is ideal for driving bus lines. the device features four output enable inputs (1 oe, 2 oe, 3 oe and 4 oe), each controlling one of the 3-state outputs. 2. features n quad bus interface n 3-state buffers n output capability: +64 ma and - 32 ma n ttl input and output switching levels n input and output interface capability to systems at 5 v supply n bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs n live insertion and extraction permitted n no bus current loading when output is tied to 5 v bus n power-up 3-state n latch-up protection: u jesd78: exceeds 500 ma n esd protection: u mil std 883 method 3015: exceeds 2000 v u machine model: exceeds 200 v 3. quick reference data 74lvt125; 74lvth125 3.3 v quad buffer; 3-state rev. 06 6 march 2006 product data sheet table 1. quick reference data gnd = 0 v; t amb =25 c. symbol parameter conditions min typ max unit t plh low-to-high propagation delay na to ny c l = 50 pf; v cc = 3.3 v - 2.7 - ns t phl high-to-low propagation delay na to ny c l = 50 pf; v cc = 3.3 v - 2.9 - ns
74lvt_lvth125_6 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 06 6 march 2006 2 of 16 philips semiconductors 74lvt125; 74lvth125 3.3 v quad buffer; 3-state 4. ordering information c i input capacitance v i = 0 v or 3.0 v - 4 - pf c o output capacitance outputs disabled; v o = 0 v or 3.0 v -8-pf i cc quiescent supply current outputs disabled; v cc = 3.6 v - 0.13 - ma table 1. quick reference data continued gnd = 0 v; t amb =25 c. symbol parameter conditions min typ max unit table 2. ordering information type number package temperature range name description version 74lvt125d - 40 c to +85 c so14 plastic small outline package; 14 leads; body width 3.9 mm sot108-1 74lvt125db - 40 c to +85 c ssop14 plastic shrink small outline package; 14 leads; body width 5.3 mm sot337-1 74lvt125pw - 40 c to +85 c tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 74lvt125bq - 40 c to +85 c dhvqfn14 plastic dual in-line compatible thermal enhanced very thin quad ?at package; no leads; 14 terminals; body 2.5 3 0.85 mm sot762-1 74lvth125d - 40 c to +85 c so14 plastic small outline package; 14 leads; body width 3.9 mm sot108-1 74LVTH125DB - 40 c to +85 c ssop14 plastic shrink small outline package; 14 leads; body width 5.3 mm sot337-1 74lvth125pw - 40 c to +85 c tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 74lvth125bq - 40 c to +85 c dhvqfn14 plastic dual in-line compatible thermal enhanced very thin quad ?at package; no leads; 14 terminals; body 2.5 3 0.85 mm sot762-1
74lvt_lvth125_6 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 06 6 march 2006 3 of 16 philips semiconductors 74lvt125; 74lvth125 3.3 v quad buffer; 3-state 5. functional diagram 6. pinning information 6.1 pinning fig 1. logic symbol fig 2. iec logic symbol fig 3. logic diagram mna228 1a 1y 2 1 3 1oe 2a 2y 5 4 6 2oe 3a 3y 9 10 8 3oe 4a 4y 12 13 11 4oe mna229 1 en1 1 3 2 4 6 5 10 8 9 13 11 12 mna227 noe na ny (1) the die substrate is attached to the exposed die pad using conductive die attach material. it can not be used as a supply pin or input. fig 4. pin con?guration so14, ssop14 and tssop14 fig 5. pin con?guration dhvqfn14 125 1oe v cc 1a 4oe 1y 4a 2oe 4y 2a 3oe 2y 3a gnd 3y 001aac476 1 2 3 4 5 6 7 8 10 9 12 11 14 13 001aac477 125 transparent top view 2y 3a 2a 3oe 2oe 4y 1y 4a 1a 4oe gnd 3y 1oe v cc 6 9 5 10 4 11 3 12 2 13 7 8 1 14 terminal 1 index area gnd (1)
74lvt_lvth125_6 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 06 6 march 2006 4 of 16 philips semiconductors 74lvt125; 74lvth125 3.3 v quad buffer; 3-state 6.2 pin description 7. functional description 7.1 function table [1] h = high voltage level; l = low voltage level; x = dont care; z = high-impedance off-state. table 3. pin description symbol pin description 1 oe 1 1 output enable input (active low) 1a 2 1 data input 1y 3 1 data output 2 oe 4 2 output enable input (active low) 2a 5 2 data input 2y 6 2 data output gnd 7 ground (0 v) 3y 8 3 data output 3a 9 3 data input 3 oe 10 3 output enable input (active low) 4y 11 4 data output 4a 12 4 data input 4 oe 13 4 output enable input (active low) v cc 14 supply voltage table 4. function table [1] control input output n oe na ny lll hh hxz
74lvt_lvth125_6 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 06 6 march 2006 5 of 16 philips semiconductors 74lvt125; 74lvth125 3.3 v quad buffer; 3-state 8. limiting values [1] the input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. 9. recommended operating conditions table 5. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage - 0.5 +4.6 v v i input voltage [1] - 0.5 +7.0 v v o output voltage output in off-state or high-state [1] - 0.5 +7.0 v i ik input clamping current v i <0v - - 50 ma i ok output clamping current v o <0v - - 50 ma i o output current output in low-state - 128 ma output in high-state - - 64 ma t stg storage temperature - 65 +150 c t j junction temperature [2] - 150 c table 6. recommended operating conditions symbol parameter conditions min typ max unit v cc supply voltage 2.7 - 3.6 v v i input voltage 0 - 5.5 v v ih high-state input voltage 2.0 - - v v il low-state input voltage - - 0.8 v i oh high-state output current - - - 32 ma i ol low-state output current none - - 32 ma current duty cycle 50 %; f 3 1 khz --64ma d t/ d v input transition rise and fall rate 0 - 10 ns/v t amb ambient temperature in free air - 40 - +85 c
74lvt_lvth125_6 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 06 6 march 2006 6 of 16 philips semiconductors 74lvt125; 74lvth125 3.3 v quad buffer; 3-state 10. static characteristics table 7. static characteristics at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit t amb = - 40 c to +85 c [1] v ik input clamping voltage i ik = - 18 ma; v cc = 2.7 v - - 0.9 - 1.2 v v oh high-state output voltage i oh = - 100 m a; v cc = 2.7 v to 3.6 v v cc - 0.2 v cc - 0.1 - v i oh = - 8 ma; v cc = 2.7 v 2.4 2.5 - v i oh = - 32 ma; v cc = 3.0 v 2.0 2.2 - v v ol low-state output voltage v cc = 2.7 v i ol = 100 m a - 0.1 0.2 v i ol = 24 ma - 0.3 0.5 v v cc = 3.0 v i ol = 16 ma - 0.25 0.4 v i ol = 32 ma - 0.3 0.5 v i ol = 64 ma - 0.4 0.55 v i li input leakage current all input pins v cc = 0 v or 3.6 v; v i = 5.5 v - 1 10 m a control pins v cc = 3.6 v; v i =v cc or gnd - 0.1 1 m a data pins v cc = 3.6 v [2] v i =v cc - 0.1 1 m a v i =0v - - 1 - 5 m a i off power-off leakage current v cc = 0 v; v i or v o = 0 v to 4.5 v - 1 100 m a i hold bus hold current data input v cc = 3 v [3] v i = 0.8 v 75 150 - m a v i = 2.0 v - 75 - 150 - m a v cc = 0 v to 3.6 v v i = 3.6 v 500 - - m a i ex external current into output output in high-state when v o >v cc ; v o = 5.5 v and v cc = 3.0 v - 60 125 m a i o(pu/pd) power-up/power-down output current v cc 1.2 v; v o = 0.5 v to v cc ; v i = gnd or v cc ; n oe = dont care [4] - 1 100 m a i oz off-state output current v cc = 3.6 v; v i =v ih or v il output high: v o = 3.0 v - 1 5 m a output low: v o = 0.5 v - - 1 - 5 m a i cc quiescent supply current v cc = 3.6 v; v i = gnd or v cc ; i o =0a outputs high - 0.13 0.19 ma outputs low - 2 7 ma outputs disabled [5] - 0.13 0.19 ma
74lvt_lvth125_6 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 06 6 march 2006 7 of 16 philips semiconductors 74lvt125; 74lvth125 3.3 v quad buffer; 3-state [1] typical values are measured at v cc = 3.3 v and t amb =25 c. [2] unused pins at v cc or gnd. [3] this is the bus hold overdrive current required to force the input to the opposite logic state. [4] this parameter is valid for any v cc between 0 v and 1.2 v with a transition time of up to 10 ms. from v cc = 1.2 v to v cc = 3.0 v to 3.6 v a transition time of 100 m s is permitted. this parameter is valid for t amb =25 c only. [5] i cc is measured with outputs pulled to v cc or gnd. [6] this is the increase in supply current for each input at the speci?ed voltage level other than v cc or gnd. 11. dynamic characteristics [1] typical values are at v cc = 3.3 v and t amb =25 c. d i cc additional quiescent supply current per input pin; v cc = 3 v to 3.6 v; one input at v cc - 0.6 v and other inputs at v cc or gnd [6] - 0.1 0.2 ma c i input capacitance v i = 0 v or 3.0 v - 4 - pf c o output capacitance outputs disabled; v o = 0 v or 3.0 v -8-pf table 7. static characteristics continued at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit table 8. dynamic characteristics voltages are referenced to gnd (ground = 0 v); for test circuit see figure 8 . symbol parameter conditions min typ max unit t amb = - 40 c to +85 c [1] t plh low-to-high propagation delay nan to ny see figure 6 v cc = 2.7 v - - 4.5 ns v cc = 3.0 v to 3.6 v 1.0 2.7 4.0 ns t phl high-to-low propagation delay nan to ny see figure 6 v cc = 2.7 v - - 4.9 ns v cc = 3.0 v to 3.6 v 1.0 2.9 3.9 ns t pzh output enable time n oe to ny see figure 7 v cc = 2.7 v - - 6.0 ns v cc = 3.0 v to 3.6 v 1.0 3.4 4.7 ns t pzl output enable time n oe to ny see figure 7 v cc = 2.7 v - - 6.5 ns v cc = 3.0 v to 3.6 v 1.1 3.4 4.7 ns t phz output disable time n oe to ny see figure 7 v cc = 2.7 v - - 5.7 ns v cc = 3.0 v to 3.6 v 1.8 3.7 5.1 ns t plz output disable time n oe to ny see figure 7 v cc = 2.7 v - - 4.0 ns v cc = 3.0 v to 3.6 v 1.3 2.6 4.5 ns
74lvt_lvth125_6 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 06 6 march 2006 8 of 16 philips semiconductors 74lvt125; 74lvth125 3.3 v quad buffer; 3-state 12. waveforms v m = 1.5 v. v ol and v oh are typical voltage output drop that occur with the output load. fig 6. propagation delay input (na) to output (ny) v m = 1.5 v. v ol and v oh are typical voltage output drop that occur with the output load. fig 7. enable and disable times of 3-state outputs mnb072 na input ny output t plh t phl gnd v i v m v m v m v m v oh v ol 001aac475 t pzl ny output ny output noe input v ol v cc v oh v i v m gnd 0 v t plz t pzh t phz v ol + 0.3 v v oh - 0.3 v v m v m
74lvt_lvth125_6 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 06 6 march 2006 9 of 16 philips semiconductors 74lvt125; 74lvth125 3.3 v quad buffer; 3-state test data is given in t ab le 9 . de?nitions test circuit: r l = load resistor. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to output impedance z o of the pulse generator. v ext = test voltage for switching times. fig 8. load circuitry for switching times table 9. test data input load v ext v i f i t w t r , t f c l r l t phz , t pzh t plz , t pzl t plh , t phl 2.7 v 10 mhz 500 ns 2.5 ns 50 pf 500 w gnd 6 v open v ext v cc v i v o 001aae235 dut c l r t r l r l pulse generator v m v m t w t w 10 % 90 % 0 v v i v i negative pulse positive pulse 0 v v m v m 90 % 10 % t f t r t r t f
74lvt_lvth125_6 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 06 6 march 2006 10 of 16 philips semiconductors 74lvt125; 74lvth125 3.3 v quad buffer; 3-state 13. package outline fig 9. package outline sot108-1 (so14) unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot108-1 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 7 8 1 14 y 076e06 ms-012 pin 1 index 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.35 0.34 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 99-12-27 03-02-19 0 2.5 5 mm scale so14: plastic small outline package; 14 leads; body width 3.9 mm sot108-1
74lvt_lvth125_6 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 06 6 march 2006 11 of 16 philips semiconductors 74lvt125; 74lvth125 3.3 v quad buffer; 3-state fig 10. package outline sot337-1 (ssop14) unit a 1 a 2 a 3 b p cd (1) e (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 1.25 0.2 7.9 7.6 1.03 0.63 0.9 0.7 1.4 0.9 8 0 o o 0.13 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. sot337-1 99-12-27 03-02-19 (1) w m b p d h e e z e c v m a x a y 1 7 14 8 q a a 1 a 2 l p q detail x l (a ) 3 mo-150 pin 1 index 0 2.5 5 mm scale ssop14: plastic shrink small outline package; 14 leads; body width 5.3 mm sot337-1 a max. 2
74lvt_lvth125_6 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 06 6 march 2006 12 of 16 philips semiconductors 74lvt125; 74lvth125 3.3 v quad buffer; 3-state fig 11. package outline sot402-1 (tssop14) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.72 0.38 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot402-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 17 14 8 q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 a max. 1.1 pin 1 index
74lvt_lvth125_6 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 06 6 march 2006 13 of 16 philips semiconductors 74lvt125; 74lvth125 3.3 v quad buffer; 3-state fig 12. package outline sot762-1 (dhvqfn14) terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 3.1 2.9 d h 1.65 1.35 y 1 2.6 2.4 1.15 0.85 e 1 2 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot762-1 mo-241 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot762-1 dhvqfn14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 26 13 9 8 7 1 14 x d e c b a 02-10-17 03-01-27 terminal 1 index area a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1)
74lvt_lvth125_6 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 06 6 march 2006 14 of 16 philips semiconductors 74lvt125; 74lvth125 3.3 v quad buffer; 3-state 14. abbreviations 15. revision history table 10. abbreviations acronym description cmos complementary metal oxide semiconductor dut device under test esd electrostatic discharge ttl transistor-transistor logic table 11. revision history document id release date data sheet status change notice supersedes 74lvt_lvth125_6 20060306 product data sheet - 74lvt125_5 (9397 750 14703) modi?cations: ? section 4 : added type numbers 74lvth125d, 74LVTH125DB, 74lvth125pw and 74lvth125bq. 74lvt125_5 20050210 product data sheet - 74lvt125_4 (9397 750 14552) 74lvt125_4 20050207 product data sheet - 74lvt125_3 (9397 750 13535) 74lvt125_3 20040624 product data sheet - 74lvt125_2 (9397 750 03514) 74lvt125_2 19980219 product speci?cation - 74lvt125_1 74lvt125_1 - - - -
74lvt_lvth125_6 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 06 6 march 2006 15 of 16 philips semiconductors 74lvt125; 74lvth125 3.3 v quad buffer; 3-state 16. legal information 16.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .semiconductors .philips .com. 16.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. philips semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local philips semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 16.3 disclaimers general information in this document is believed to be accurate and reliable. however, philips semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes philips semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use philips semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a philips semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. philips semiconductors accepts no liability for inclusion and/or use of philips semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale philips semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .semiconductors .philips .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by philips semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. 17. contact information for additional information, please visit: http://www.semiconductors.philips.com for sales of?ce addresses, send an email to: sales.addresses@www.semiconductors.philips.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
philips semiconductors 74lvt125; 74lvth125 3.3 v quad buffer; 3-state ? koninklijke philips electronics n.v. 2006. all rights reserved. for more information, please visit: http://www.semiconductors.philips.com. for sales office addresses, email to: sales.addresses@www.semiconductors.philips.com. date of release: 6 march 2006 document identifier: 74lvt_lvth125_6 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 quick reference data . . . . . . . . . . . . . . . . . . . . . 1 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 4 7.1 function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 recommended operating conditions. . . . . . . . 5 10 static characteristics. . . . . . . . . . . . . . . . . . . . . 6 11 dynamic characteristics . . . . . . . . . . . . . . . . . . 7 12 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 16 legal information. . . . . . . . . . . . . . . . . . . . . . . 15 16.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 16.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 16.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 16.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 17 contact information. . . . . . . . . . . . . . . . . . . . . 15 18 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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